Regviz

Cypress Semiconductor /psoc63 /BLE /BLELL /LL_DBG_6

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as LL_DBG_6

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/BLE/BLELL/LL_DBG_6#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADV_TX_WR_PTR 0SCAN_RSP_TX_WR_PTR 0ADV_TX_RD_PTR

Description

LL debug register 6

Fields

ADV_TX_WR_PTR

Advertiser Transmit FIFO write pointer
SCAN_RSP_TX_WR_PTR

Scan Response Transmit FIFO write pointer
ADV_TX_RD_PTR

Advertiser/ Scan Response FIFO read pointer

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data